The invention relates to charge storage memory systems of the type requiring periodic refreshing of the main memory array to restore the contents thereof. The memory array typically is comprised of a plurality of individual cells, arranged in rows and columns, and whose binary contents are dependent on the capacitive charge that is stored therein. The charge being stored between the substrate and gate of a field effect transistor, on a capacitor having one or more associated transistors or in some other charge storage structure. Such a memory is described in White, Jr. et al., U.S. Pat. No. 4,207,618 and in Dennard, U.S. Pat. No. 3,387,286. Dennard disclosing a metal oxide semiconductor random access memory (MOSRAM) and its operation, as well as the need for periodically refreshing the charge stored in the cells; and White disclosing a 65K MOSRAM having on-chip provisions for an address counter and multiplexing circuitry to select from normal and refresh accesses. The refresh time for such memories, however, typically occupies 10% to 20% of the usable time of the memory with a complete refresh operation being performed at least once during the device' s refresh requirement interval (RRI).
The necessity to accommodate the RRI, however, presents a number of problems to a memory system designer when he is attempting to maximize a system's operating time. It is therefore desirable to minimize the necessity of the refresh operation by relegating it to non-active memory time and by taking advantage of the fact that as each row is normally accessed, it is refreshed. Previous solutions to the problem have been achieved by a variety of techniques; such as refreshing the entire memory array at one time in a "burst" mode (e.g. Dennard), interleaving the refresh and normal access operations (e.g. Anderson, Jr. et al., U.S. Pat. No. 3,811,117) and refreshing in parallel with normal access operations (e.g. U.S. Pat. No. 3,859,640).
The general interleaving technique taught by Anderson presents a desired solution, but it suffers in that excessive circuitry is required to accommodate the "least recently used" criteria. Anderson teaches the use of an address age memory and a comparator, but because of the added cost in associated circuitry (i.e. a counter and detector for each row of cells of the array), such a technique becomes cost prohibitive as the size of the memory array expands from the described 1K array to a 16K, 64K or 256K array, as evidenced by White. And even if the array were fabricated as an integrated circuit, such a technique would require a great deal of space on the surface of the die," which space is not accommodated in commercially available devices.
It is therefore an object of the present invention to minimize the impact of the refresh degradation of a main memory system's through-put in a cost efficient manner, using readily available devices.
It is an additional object to refresh the system's main memory array on an "if required" basis. Which objective is achieved with the aid of a refresh flag memory (RFM) that monitors each of the memory array's normal access operations during the RRI and flags the address in the RFM that corresponds to the accessed address. Thus a record is maintained of all accessed addresses during the operating period so that the system need only refresh those addresses which were not previously accessed. The total refresh time for any RRI can therefore be maintained at a minimum, especially in active systems having a majority of the addresses accessed during the RRI.